BRE440A™ Radiation Hardened Processor System on a Chip (SOC)

The BRE440A Central Processing Unit (CPU) is a fully radiation hardened implementation of the PowerPC 440 processor core in a true System-On-A-Chip (SOC) design, including floating point unit. It meets the requirements for a wide variety of high reliability space and missile applications. 

 

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Overview

The BRE440A SOC CPU integrates a mix of peripheral controllers by implementing IBM’s high speed CoreConnect™ technology and contains the PPC440x5 version of the PPC440 core. The embedded processor provides high performance and low power consumption. The BRE440A SOC CPU executes at sustained speeds approaching two instructions per cycle. On-chip peripherals reduce chip count and design complexity in systems and improve system throughput. The 440 core combined with wide peripheral mix provides an ideal foundation for compact systems.

The BRE440A is the next generation of the BRE440 SOC CPU architecture which has extensive flight heritage and is currently on-orbit performing its mission on several spacecraft. This revision is designed to provide the highest level of radiation hardened processing available for spacecraft, missiles, and launch vehicles.

Specifications

 

Features
High Performance IBM PPC440 Core, 2 MIPS/MHz
ANSI/IEEE 754-1985 compliant FPU
Manufactured on Honeywell 150nm HX5000 Radiation Hardened ASIC Line
Superscalar, Dual Issue, 32-bit RISC, Book E Compliant
Secure and Trusted Boot with AES256 Encryption (Pending) 

 

 

 

Memory
32 kByte L1 Instruction & Data Caches
256 kByte unified L2 Cache (can be configured as general purpose SRAM)
On-Chip 8 kByte SRAM
High Bandwidth Main Memory Access with Error Detection and Correction

 

 

 

Radiation Capability
TID >1 MRad; Latch-up immune
SEU >40 Years/Upset (Adams 90% worst case environment) 

 

 

 

Interfaces
PCI Interface for Peripheral Communication
PCI Arbitration for up to 6 External Peripherals (Clock Distribution)
4 Channel DMA with Scatter/Gather Capability
32-Bit Peripheral Bus with EDAC
32-Bit DDR DRAM Bus with EDAC
External Expansion Bus
2 Ethernet Media Access Controllers
2 UART Ports (16750 Compatible)
JTAG

 

 

 

Core Clock Frequency
300 MHz @ -55°C to 125°C
330 MHz @ -10°C to 80°C
Typical Power 8.0W @ 330MHz
Typical Power 3.5W @ 240MHz